Show HN: Dotenv Mask Editor: No more embarrassing screen leaks of your .env https://ift.tt/ElUmgvK

Show HN: Dotenv Mask Editor: No more embarrassing screen leaks of your .env Hi HN, I built this because I often work in coworking spaces or do screen sharing, and I've always had this fear of accidentally flashing my .env file with production secrets to the whole room (or recording). It’s a simple VS Code extension that opens .env files in a custom grid editor. It automatically masks any value longer than 6 characters so I can safely open the file to check keys without exposing the actual secrets. It runs 100% locally with zero dependencies (I know how sensitive these files are). It just reads the file, renders the grid, and saves it back as standard text. It's open source (MIT) and I'd love any feedback on the masking logic or other features that would make it safer to use. Marketplace: https://marketplace.visualstudio.com/items?itemName=xinbenlv... Github https://ift.tt/tI6RAiM https://marketplace.visualstudio.com/items?itemName=xinbenlv.dotenv-mask-editor January 21, 2026 at 09:04PM

Show HN: Open-source certificate from GitHub activity https://ift.tt/hTbnzAC

Show HN: Open-source certificate from GitHub activity I built this as a small side project to learn and experiment, and I ended up with this! I used a subdomain from my personal portfolio, and everything else runs on free tiers. The project uses Nuxt, SVG, Cloudflare Workers, D1 (SQL), KV, Terraform, and some agentic coding with OpenAI Codex and Claude Code. What started as a joke among friends turned into a fun excuse to build something end to end, from zero to production, and to explore a few things I’d never touched before. I’d really appreciate any feedback or suggestions. https://ift.tt/pnRD0tV January 18, 2026 at 12:52PM

Show HN: SKILL.md Hub https://ift.tt/H5vXGmb

Show HN: SKILL.md Hub https://openskills.space January 21, 2026 at 04:07AM

Show HN: LLM fine-tuning without infra or ML expertise https://ift.tt/p0Ctzcv

Show HN: LLM fine-tuning without infra or ML expertise https://www.tinytune.xyz/ January 21, 2026 at 04:57AM

Show HN: Parallel Agentic Search on the Twitter Algorithm https://ift.tt/JMiQ2S5

Show HN: Parallel Agentic Search on the Twitter Algorithm https://ift.tt/pVOB1H6 January 20, 2026 at 07:42PM

Show HN: Explic – An AI tutor that prompts you with questions, not answers https://ift.tt/9EnrFcT

Show HN: Explic – An AI tutor that prompts you with questions, not answers https://www.explic.app/ January 20, 2026 at 06:08AM

Show HN: E80: an 8-bit CPU in structural VHDL https://ift.tt/0k5LjCI

Show HN: E80: an 8-bit CPU in structural VHDL I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ? Well, it did and it works nicely. No arithmetic libraries, no PROCESS except for the DFF component (obviously). Of course it's a bit of a "resource hog" compared to optimized cores, (eg. the RAM is build out of flip flops instead of a block ram that takes advantage of FPGA intermal memory) but you can actually trace every signal through the datapath as it happens. I also build an assembler in C99 without external libraries (please be forgiving, my code is very primitive I think). I bundled Sci1 (Scintilla), GHDL and GTKWave into a single installer so you can write assembly and see the waveforms immediately without having to spend hours configuring simulators. Currently Windows only, but at some point I'll have to do it on Linux too. I tested it on the Tang Primer 25K and Cyclone IV, and I included my Gowin, Quartus and Vivado projects files. That should make easy to run on your FPGA. Everything is under the GPL3. (Edit: I did not use AI. Not was it a waste of time for the VHDL because my design is too novel -- but even for beta testing it would waste my time because those LLMs are too well trained for x86/ARM and my flag logic draws from 6502/6800 and even my ripple carry adder doesn't flip the carry bit in subtraction. Point is -- AI couldn't help. It only kept complaining that my assembler's C code wasn't up to 2026 standards) https://ift.tt/k4vMjm6 January 17, 2026 at 06:39PM